Introduction to Advanced System-on-Chip Test Design and Optimization
By Erik Larsson

Index

A

ABM 63
Abort-on-fail 160
abort-on-fail 277
Address decoder fault 46
Algorithmic Test Sequence 47
Aliasing 43
Alternating run-length codes 80
Analog Boundary Module (ABM) 63
Analog test access port 63
Analog test bus (ATB) 61
Analog testing 52
ATAP 63
ATB 61
ATE 77, 291
ATE Advantest 78
ATE Agilent (HP) 78
ATE channel 78
ATE clock-domains 78
ATE Credence 78
ATE LTX 78
ATE Refill 79
ATE sequencer 80
ATE Teradyne 78
ATS 48

B

Backtracking 16
Bandwidth assignment 152
Bandwidth limitation 217
Bandwidth limitations 78, 152
Bed-of-nails tester 53, 61
BILBO (Built-In Logic Block Observer) 43
Block 68
Block Diagrams 6
Boolean Difference 25
Bottleneck 15, 159
Boundary Scan 100
Boundary Scan Cell 56
Boundary-Scan 53
Boundary-scan 99
Boundary-Scan Description Language 58
Branch-and-bound 16
Bridging fault 46
Bridging Fault Model 22
Broadside Test 37
BSDL 58
Built-In Logic Block Observer 43
Bypass 57

C

CAD 5
Care bit 79
Central processing unit 68
Checkboard test 47
Chromosome 18
Circular BIST 43
Clamp 57
Clock signal distribution 21
Combinational 25
Computational cost 1, 15
Computational quality 15
Concurrent test scheduling 116
Continuos values 61
Control pins 138
Controlability 32
Core 7, 68
Core integrator 7, 157
Core providers 7
Core test integrator 7, 157
Core Test Language 102
Core Transparancy 112
Core-based design 7, 164
Cost function 115
Cost-per-transistor 2
Coupling fault 45
CPU 68
Critical path 23
Cross-core testing 84
Crossover process 18
Cycle time (Tc) 10

D

Daisy chaining 50
Daisychain Architecture 110
Daisy-chain testing 117
Copyright Springer 2005 under license agreement with Books24x7
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