TABLE OF CONTENTS Test power consumption and test time minimization (test scheduling) are becoming major challenges when developing test solutions for core-based designs. Test power consumption is usually high during testing since it is desirable to activate as many fault locations as possible in a minimum of time, and if the tests are scheduled concurrently in order to reduce the testing times the test power increases. In this chapter, we demonstrate that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines, and we make use of an existing preemptive scheduling algorithm and reconfigurable core wrappers to produce optimal solution in linear time. We propose a novel reconfigurable power-conscious core test wrapper and discusses its application to optimal power-constrained SOC (system-on-chip) test scheduling. The advantage of the proposed wrapper is that at each core it allows (1) a variable number of wrapper-chains, and (2) a possibility to select the appropriate test power consumption for each core. Our scheduling technique produces optimal solutions in respect to test time, and selects wrapper configurations in a systematic way that implicitly minimizes the TAM routing and the wrapper logic. We have implemented the technique and the experimental results show the efficiency of our approach. The results from our technique are less than 3% from the theoretical computed lower bound.
Long testing times are required due to the increasing amount of test data needed to test complex SOC (System-on-Chip). The testing times can be reduced by...
