TABLE OF CONTENTS Testing is performed to ensure the manufacturing of fault-free chips. As the number of possible faults in a chip is increasing dramatically due to the technology development, the testing process and the test design are becoming complicated and very expensive, especially in the case of SOCs. It is therefore important to take test design into consideration as early as possible in the SOC design flow in order to develop an efficient test solution. In this chapter, we propose a technique to integrate test design in the early design exploration process. The technique can, in contrast to previous approaches, be used already in the core selection process to evaluate the impact on the system's final test solution imposed by different design decisions, regarding the selection of cores and their test characteristics. The proposed technique considers the interdependent problems of core selection, test scheduling, TAM (test access mechanism) design, test set selection, and test resource floor-planning. It minimizes a weighted cost-function based on test time and TAM routing cost while considering test conflicts and test power limitations. The power consumed during testing is often higher than that during normal operation since during testing hyper-activity is desired in order to maximize the number of tested faults at a minimal time. A system under test can actually be damaged during testing, and therefore power constraints must be considered. However, power consumption is complicated to model, and often simplistic models that focus only on the global system power limit have been proposed...
