TABLE OF CONTENTS In this chapter we discuss modeling and concepts related to core-based system. The introduction of test methods (DFT techniques), the creation of test stimulus, and the test response analysis in Chapter Design for Test on page 5 serves as the basis for this chapter. It is therefore known that a testable unit has its test stimulus and expected test response. The site where the test stimulus (test vectors, test patterns) is stored or created is called test source while a test sink is where the test response is stored or analyzed (Figure 55). Figure 55 shows a test architecture where test stimulus is stored at the test source and transported on the test access mechanism (TAM) to the testable unit, in this example a core. The test response is also transported on the TAM to the test sink. In order to ease test access between the core and the TAM the core is placed in a wrapper.
These concepts have been introduced by Zorian et al. [289]. We further illustrate them with the example in Figure 56. The example consists of three main blocks of logic, core A (CPU core), core B (DSP core), and core C (UDL (user-defined logic) block). A test source is...
