[1] M.S.Abadir and H.K.Reghabati, Functional Testing of Semiconductor Random Access Memories , Computer Survey, Vol. 15, No. 3, 1983, pages 175 198.

[2] M.Abramovici, M.A.Breuer, and A.D.Friedman, Digital Systems Testing and Testable Design, IEEE Press, ISBN 0 7803 1062 4, 1990.

[3] R.D.Adams, High Performance Memory Testing Design Principles, Fault Modeling and Self-Test , Kluwer Academic Publisher, ISBN 1 4020 7255 4, 2003.

[4] Advantest, http://www.advantest.com/

[5] J.Aerts and E.J.Marinissen, Scan Chain Design for Test Time Reduction in Core-Based ICs , Proceedings of International Test Conference (ITC) , Washington, DC, USA, October 1998, pages 448 457.

[6] A.V.Aho, J.E.Hopcroft and J.D.Ullman, Data Structures and Algorithms, Addison-Wesley, 1983, ISBN 0 201 00023 7.

[7] Agilent (HP), http://www.agilent.com/

[8] P.H.Bardell, W.H.McAnney, and J.Savir, Built-In Test for VLSI Pseudorandom Techniques , John Wiley and Sons, 1987.

[9] J.Barwise and J.Etchemendy, The Language of First-Order Logic, CSLI Publications, ISBN 0 937073 99 7, 1993.

[10] I.Bayraktarolgu and A.Orailoglu, Test Volume And Application Time Reduction Through Scan Chain Concealment , Proceedings of Design Automation Conference (DAC) , Las Vegas, NV, USA, June 2001, pages 151 155.

[11] F.Beenker, B.Bennets, and L.Thijssen, Testability Concepts for Digital ICs The Macro Test Approach , Frontiers in Electronic Testing , vol. 3, Boston, Kluwer, 1995.

[12] M.Benabdenbi, W.Maroufi, and M.Marzouki, CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing , Journal of Electronic Testing; Theory and Applications (JETTA) , Vol. 18, Nos. 4/ 5, August/October 2002, pages 455 472.

[13] M.J.Bending, Hitest: A Knowledge-Based Test Generation System , Design & Test of Computers , Vol. 1, May 1984, pages 83 92.

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