Part 3: Soc Test Applications

CHAPTER LIST

Chapter 10: A Reconfigurable Power-Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling
Chapter 11: An Integrated Framework for the Design and Optimization of SOC Test Solutions
Chapter 12: Efficient Test Solutions for Core-Based Designs
Chapter 13: Core Selection in the SOC Test Design-Flow
Chapter 14: Defect-Aware Test Scheduling
Chapter 15: An Integrated Technique for Test Vector Selection and Test Scheduling under ATE Memory Depth Constraint

Part 3 is a collection of the following longer papers:

The chapter A Reconfigurable Power-Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling is based on the papers presented at International Test Conference (ITC 03) [171], Asian Test Symposium (ATS 0303) [172], and Workshop on RTL and High-Level Testing WRTLT 02 [167].
The chapter An Integrated Framework for the Design and Optimization of SOC Test Solutions is based on the papers presented at Design Automation and Test in Europe (DATE), 2001 [158], International Conference on Computer-Aided Design (ICCAD), 2001 [160], and Journal on Electronic Testing: Theory and Applicationd (JETTA) 2002 [164, 165].
The chapter Efficient Test Solutions for Core-Based Designs is based on the following papers Asian Test Symposium (ATS), 2002 [166], and Transactions on Coputer-Aided Design for Integrated Circuits, 2004 [176].
The chapter Integrating Core Selection in the System-on-Chip Test Solution Design-Flow is based on the papers presented at International Test Resource Workshop (TRP), 2004, [175], and International Test Conference (ITC), 2004 [177].
The chapter Defect-Aware Test Scheduling is based on the papers presented at International Test Synthesis Workshop (ITSW 03)...

< Previous Excerpt Next Excerpt >

Purchase This Book