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Type:

Triggering:

Output Characteristics:

Supply Voltage:

Propagation Delay:

Maximum Clocking Frequency (fMAX):

Power Dissipation (PD):

Operating Current:

Low Level Output Current (Sink):

High Level Output Current (Source):

Operating Temperature:

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Pin Count:

Number of Units in the Chip:

Features:

Help with Flip-Flops specifications:

Flip-Flops Specifications
   Type       
   Your choices are...         
   D       D flip-flops have one input called D (data) and two outputs called Q and Q’. D flip-flops are pulsed with a clock. The D input is sampled during the clock pulse. If D = 1 when sampling occurs, the flip-flop is switched to the set state (Q = 1) unless it was already set. If D = 0, then the flip-flop switches to the clear or reset state (Q = 0). With D flip-flops, the no-change condition is attained only when there is no change to the D input. 
   S-R       S-R flip-flops have S (Set) and R (Reset) inputs. SC flip-flops have S (Set) and C (Clear) inputs.  There are two types of S-R flip-flops: Active High and Active Low. Like all flip-flops, both types of S-R devices are pulsed with a clock. Depending on the input values, the two complementary outputs (Q and Q’) change according to the flip-flop’s logical function at the moment of the clock input’s active transition.  If the S-R flip-flop is an Active High device: If S = 1 and R = 0, then Q = 1 and the state is Set. If S = 0 and R = 1, then Q = 0 and the state is either Reset or Clear. If S = 0 and R = 0, then there is no change in the output condition. The condition S = 1 and R = 1 is an indeterminate state to avoid since a flip-flop cannot be set and reset simultaneously. If the S-R flip-flop is an Active Low device: If S = 0 and R = 1, then Q = 1 and the state is Set. If S = 1 and R = 0, then Q = 0 and the state is either Reset or Clear. If S = 1 and R = 1, there there is no change in the output condition. The condition S = 0 and R = 0 is an indeterminate state to avoid since a flip-flop cannot be set and reset simultaneously. 
   J-K       J-K flip-flops are a variant of S-R flip-flops in that they define the S-R type’s indeterminate state. J-K flip-flops have J (Set) and K (Clear or Reset) inputs and are pulsed with a clock.  If J = 1 and K = 0, then Q = 1 and the state is Set If J = 0 and K = 1, then Q = 0 and the state is Reset or Clear If J = 0 and K = 0, there is no change in the output condition and the state is No Change If J = 1 and K = 1, then the flip-flop switches (toggles) to its complement state so that, for example, Q switches from 0 to 1 or from 1 to 0. 
   T       T (Toggle) flip-flops are a single input version of the J-K flip-flop. T flip-flops are obtained from J-K flip-flops when both inputs are tied together. The output of the T flip-flop toggles with each clock pulse. This type of flip-flop is used to develop counters, registers, and other similar devices. 
   Other       Other unlisted flip-flop types. 
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   Triggering       
   Your choices are...         
   Negative-edge Triggered       With negative-edge triggered flip-flops, the output can change only the clock's negative edges.     
   Positive-edge Triggered       With positive-edge triggered flip-flops, the output can change only the clock's positive edges. 
   Master-slave       Master-slave flip-flops read the input values on the clock’s positive edges, but allow the output to respond on only the clock’s negative edges. Master-slave flip-flops are also known as pulse-triggered flip-flops. The term “pulse-triggered” denotes that data is entered on the rising edge of the clock pulse, but that the output does not reflect the input state until the clock pulse’s falling edge. Master-slave flip-flops are sensitive to any changes in input level when the clock pulse is high. Therefore, the inputs must be set before the rising edge and remain unchanged until the falling edge. 
   Other       Other unlisted triggering styles. 
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   Output Characteristics       
   Your choices are...         
   3-State Output       Flip-flops have a 3-state output buffer. 
   Open-Collector Output       Open-collector outputs are connected internally to the collector of a bipolar transistor. 
   Open-Drain Output       Open-drain outputs are connected internally to the drain of a field-effect transistor. 
   Output Enable Input (OE)       Output enable (OE) inputs have an enable pin for the output. 
   Complementary Output       Devices with a pin for a complementary output have two outputs: the true output and the complementary output.  
   Other       Other unlisted output types. 
   Search Logic:      All products with ANY of the selected attributes will be returned as matches. Leaving all boxes unchecked will not limit the search criteria for this question; products with all attribute options will be returned as matches.
   Supply Voltage       
   Your choices are...         
   -5 V       Chips operate with -5 volts. 
   -4.5 V       Chips operate with -4.5 volts. 
   -3.3 V       Chips operate with -3.3 volts. 
   -3 V       Chip operate with -3 volts. 
   1.2 V       Chips operate with 1.2 volts. 
   1.5 V       Chips operate with 1.5 volts. 
   1.8 V       Chips operate with 1.8 volts. 
   2.5 V       Chips operate with 2.5 volts. 
   3 V       Chips operate with 3 volts. 
   3.3 V       Chips operate with 3.3 volts. 
   3.6V       Chips operate with 3.6 volts. 
   5 V       Chips operate with 5 volts. 
   Other       Other unlisted supply voltages. 
   Search Logic:      All products with ANY of the selected attributes will be returned as matches. Leaving all boxes unchecked will not limit the search criteria for this question; products with all attribute options will be returned as matches.
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Performance
   Propagation Delay:       The propagation delay is the time interval between the application of an input signal and the occurrence of the corresponding output in a logic circuit. 
   Search Logic:      All matching products will have a value less than or equal to the specified value.
   Maximum Clocking Frequency (fMAX)       The maximum clocking frequency (fMAX) is the highest rate in hertz (Hz) at which flip-flops can be triggered reliably. fMAX is applied to the flip-flop’s clock (CLK) input. 
   Search Logic:      User may specify either, both, or neither of the "At Least" and "No More Than" values. Products returned as matches will meet all specified criteria.
   Power Dissipation (PD)       The power dissipation is the total power consumption of the device and is generally expressed in watts (W) or millwatts. 
   Search Logic:      All matching products will have a value less than or equal to the specified value.
   Operating Current       The operating current is the minimum current needed for active chip operation. 
   Search Logic:      All matching products will have a value less than or equal to the specified value.
   Low Level Output Current (Sink)       The low-level output current (IOL) is the output current to which  gates sink when the output is at a low level. 
   Search Logic:      All matching products will have a value less than or equal to the specified value.
   High Level Output Current (Source)       The high-level output current (IOH) is the output current that gates source to a load when the output is at a high level. 
   Search Logic:      All matching products will have a value less than or equal to the specified value.
   Operating Temperature:       This is the full-required range of ambient operating temperatures. 
   Search Logic:      User may specify either, both, or neither of the limits in a "From - To" range; when both are specified, matching products will cover entire range. Products returned as matches will meet all specified criteria.
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IC Chip Specifications
   IC Package Type       
   Your choices are...         
   SSOP       Shrink small outline package (SSOP). 
   TSSOP       Thin shrink small outline L-leaded package (TSSOP). 
   TVSOP       Thin very small outline package (TVSOP). 
   SOJ       Small outline J-lead (SOJ) is a common form of surface-mount DRAM packaging. It is a rectangular package with J-shaped leads on the two long sides of the device. 
   HSOF       Small outline flat-leaded package with heat sink (HSOF). 
   PLCC       Plastic leaded chip carrier (PLCC). 
   LCCC       Leadless ceramic chip carrier (LCCC). 
   DIP       Dual in-line package (DIP) is a type of DRAM component packaging. DIPs can be installed either in sockets or permanently soldered into holes extending into the surface of the printed circuit board. 
   PDIP       Plastic dual in-line package (PDIP) is widely used for low cost, hand-insertion applications including consumer products, automotive devices, logic, memory ICs, micro-controllers, logic and power ICs, video controllers commercial electronics and telecommunications. 
   CDIP       Ceramic dual in-line package (CDIP) consists of two pieces of dry pressed ceramic surrounding a "DIP formed" lead frame. The ceramic / LF / ceramic system is held together hermetically by frit glass reflowed at temperatures between 400° - 460° centigrade. 
   SIP       Single in-line package (SIP). 
   SDIP       Shrink dual in-line package (SDIP). 
   SZIP       Shrink zigzag in-line package (SZIP). 
   BGA       Ball-grid array (BGA) places output pins in a solder ball matrix. Generally, BGA traces are fabricated on laminated (BT-based) substrates or polyimide-based films. Therefore, the entire area of substrates or films can be used to route the interconnection. BGA has another advantage of lower ground or power inductance by assigning ground or power nets via a shorter current path to PCB. Thermally enhanced mechanisms (heat sink, thermal balls, etc.) can be applied to BGA to reduce the thermal resistance. The sophisticated capabilities make BGA the desirable package to implement electrical and thermal enhancement in response to the need for high power and high speed ICs. 
   PBGA       Plastic ball-grid array (PBGA) is the general terminology for the BGA package adopting plastic (epoxy molding compound) as the encapsulation. According to JEDEC standard, PBGA refers to an overall thickness of over 1.7mm. 
   TBGA       Tape ball-grid array (TBGA) uses a fine, polyimide substrate and provides good thermal performance with high pin counts. 
   FLGA       Fine-pitch land-grid array (FLGA) is extremely compact and lightweight, making it suitable for miniature disc drives and digital cameras. 
   QFP       Quad flat packages (QFP) contain a large number of fine, flexible, gull wing shaped leads. Lead width can be as small as 0.16 mm. Lead pitch is 0.4 mm. QFPs provide good second-level reliability and are used in processors, controllers, ASICs, DSPs, gate arrays, logic, memory ICs, PC chipsets, and other applications.  
   LQFP       Low quad flat package (LQFP). 
   TQFP       Thin quad flat package (TQFP). 
   SOP       Small outline package (SOP). 
   SOIC       Small outline integrated circuit (SOIC). 
   TSOP Type I, II       Thin small outline package (TSOP) is a type of DRAM package that uses gull wing shaped leads on both sides. TSOP DRAM mounts directly on the surface of the printed circuit board. The advantage of the TSOP package is that it is one-third the thickness of an SOJ package. TSOP components are commonly used in small outline DIMM and credit card memory applications. Thin small outline package may be Type I or Type II. 
   Other       Other unlisted, specialized, or proprietary IC packages. 
   Search Logic:      Products with the selected attribute will be returned as matches. Leaving or selecting "No Preference" will not limit the search criteria for this question; products with all attribute options will be returned as matches.
   Logic Family       
   Your choices are...         
   Transistor-Transistor Logic (TTL)       Transistor-transistor logic (TTL) is a class of digital circuits built from bipolar junction transistors (BJT), diodes and resistors. It is notable, as it was the base for the first widespread semiconductor integrated circuit (IC) technology. All TTL circuits operate with a 5 V power supply. TTL signals are defined as "low" or L when between 0 V and 0.8 V with respect to the ground terminal, and "high" or H when between 2 V and 5 V. The first logic devices designed from bipolar transistors were referred to as standard TTL. The addition of Schottky diodes to the base collector of bipolar transistor was called Schottky logic (S-TTL). Schottky diodes shorten propagation delays within TTL by preventing the collector from going into what is called “deep saturation.”  Other TTL technologies include low-power Schottky (LS-TTL), advanced Schottky (AS-TTL), advanced low-power Schottky (ALS-TTL), and low-voltage TTL (LVTTL). 
   FAST       Fairchild advanced Schottky TTL (FAST) technology was created in late 1970 when advances in IC technology allowed the speed and drive of S-TTL to be combined with the lower power of LS-TTL to form a new logic. An advanced related family is the FASTr, which is faster then FAST, has a higher driving capability (IOL, IOH), and produces much lower noise. The “r” in FASTr refers to the various speed grades, such as A, B and C, where an “A” designation means low speed and “C” means high speed. 
   Standard CMOS / CMOS 4000       Complementary metal-oxide semiconductor (CMOS) logic uses a combination of p-type and n-type metal-oxide-semiconductor field effect transistors (MOSFET) to implement logic gates and other digital circuits found in computers, telecommunications and signal processing equipment. It is the technology of choice for many present-day digital integrated circuits. CMOS 4000 refers to the series 4000 that is true CMOS with non-TTL levels. 
   Fast CMOS       Fast CMOS technology (FCT) was introduced in 1986. With this technology the speed gap between CMOS and TTL was closed. Since FCT is the CMOS version of FAST, it has the low power consumption of CMOS but speed comparable with TTL. Advanced versions of the FCT standard are FCTx and FCTx-T. The x in FCTx and FCTx-T refers to the various speed grades, such as A, B and C, where an “A” designation means low speed and “C” means high speed. 
   High-Speed CMOS       High-speed CMOS technology (HCMOS) is also known as HC / HCT. There are several basic flavors of HCMOS technology: high-speed CMOS (HC), high-speed CMOS with TTL input (HCT), advanced high-speed CMOS (AHC), and advanced high-speed CMOS with TTL inputs (AHCT). 
   Advanced CMOS       Advanced CMOS is a much higher speed version of HCMOS.  It is also known as AC / ACT.  Advanced CMOS technology comes in different flavors: standard advanced CMOS (AC), advanced CMOS with TTL inputs (ACT), advanced CMOS with quiet outputs (ACQ), advanced CMOS with TTL inputs and quiet outputs (ACTQ), advanced ultra-Low voltage CMOS (AUC), advanced ultra-low power CMOS (AUP), advanced very-low voltage CMOS (AVC), advanced low voltage HCMOS (ALVC), and advanced low voltage CMOS with bus hold (ALVCH).  ACQ / ACTQ are second generation Advanced CMOS with much lower noise. While ACQ has the CMOS input level, ACQT is equipped with TTL level input. 
   Low Voltage CMOS       There are several low voltage CMOS technologies: standard low voltage (LV), low voltage high performance HCMOS (LVC), low voltage CMOS technology with TTL inputs (LVT), Low voltage with TTL inputs and high impedance (LVTC), advanced low voltage CMOS with bus hold (ALVCH), low voltage CMOS that operates with 3 V or 5 V (LCX), and low voltage CMOS that operates with 1.8 V or 3.6 V (VCX). 
   BiCMOS       BiCMOS is a SiGe Bipolar technology that combines the high speed of bipolar TTL with the low power consumption of CMOS. There are a number of BiCMOS flavors including advanced BiCMOS technology (ABT), advanced BiCMOS technology with enhanced transceiver logic (ABTE), advanced low-voltage BiCMOS (ALB), advanced low-voltage BiCMOS technology (ALVT), BiCMOS with TTL inputs (BCT), BiCMOS with backplane and transceiver logic (BTL), and low-voltage BiCMOS technology (LVT). 
   Emitter Coupled Logic (ECL)       Emitter coupled logic (ECL) uses transistors to steer current through gates that compute logical functions. By comparison, TTL and related families use transistors as digital switches, where the transistors are either cut off or saturated, depending on the state of the circuit. This distinction explains ECL's chief advantage: that because the transistors are always in the active region, they can change state very rapidly, so ECL circuits can operate at very high speed; and also its major disadvantage: the transistors are continually drawing current, which means the circuits require high power, and thus generate large amounts of waste heat. ECL gates use differential amplifier configurations at the input stage. A bias configuration supplies a constant voltage at the midrange of the low and high logic levels to the differential amplifier, so that the appropriate logical function of the input voltages will control the amplifier and the base of the output transistor. The propagation time for this arrangement can be less than a nanosecond. Other noteworthy characteristics of the ECL family include the fact that the large current requirement is approximately constant, and does not depend significantly on the state of the circuit. This means that ECL circuits generate relatively little power noise, unlike many other logic types that typically draw far more current when switching than quiescent, for which power noise can become problematic. ECL circuits operate with negative power supplies, and logic levels incompatible with other families, which means that interoperation between ECL and other designs are difficult. The fact that the high and low logic levels are relatively close mean that ECL suffers from small noise margins, which can be troublesome in some circumstances. 
   Integrated Injection Logic (I2L)       Integrated injection logic (I2L) is based on bipolar transistor logic. It is commonly referred to as "I-square-L." 
   Silicon on Sapphire (SOS)       Silicon on sapphire (SOS) is a hetero-epitaxial process wherein a thin layer of silicon is “grown” on a sapphire (Al2O3) wafer. SOS is part of the silicon on insulator (SOI) family of CMOS technologies. SOS is primarily used in military and space applications because of its inherent resistance to radiation. It has seen little commercial use to date because of difficulties in fabricating the very small transistors used in modern high-density applications. Problematically, the SOS process often results in the formation of dislocations from crystal lattice disparities between the sapphire and silicon.  This leads to unusable wafers and drives up the production cost. 
   Gallium Arsenide (GaAs)       Gallium arsenide (GaAs) is a compound semiconductor mixing the strength of two elements, gallium (Ga) and arsenic (As). Gallium is a byproduct of the smelting of other metals, notably aluminum and zinc, and is rarer than gold. Arsenic is not rare, but it is poisonous. Gallium arsenide has many uses including being used in some diodes, field-effect transistors (FETs), and integrated circuits (ICs). GaAs components are useful at ultra-high radio frequencies and in fast electronic switching applications. GaAs devices generate less noise than most other types of semiconductor components and, as a result, are useful in weak-signal amplification applications. Gallium arsenide is used in the manufacture of light-emitting diodes (LEDs), which are found in optical communications and control systems. Gallium arsenide can replace silicon in the manufacture of linear and digital ICs. Digital devices are used for electronic switching, and also in computer systems. 
   Crossbar Technology (CBT)       Crossbar technology (CBT) enables a bus interface to function as a very fast bus switch, isolating the bus when the switch is open and offering very little delay when the switch is closed. Opening the switch provides circuit isolation (high impedance). Closing the switch provides a near-zero propagation delay through a 5-Ohm resistance. Bus switch technology is used in programmable logic devices (PLDs) for improved performance. Typically, CBT devices operate from 4.5 V to 5.0 V. CBT is also known as quick switch (QS), fast switch technology (FST), or Pericom Interface (PI5C). 
   Gunning Transceiver Logic (GTL)       Gunning transceiver logic (GTL) is a standard for electrical signals in CMOS circuits that is used to provide high data transfer speeds with small voltage swings. 
   Other       Other unlisted logic families. 
   Search Logic:      All products with ANY of the selected attributes will be returned as matches. Leaving all boxes unchecked will not limit the search criteria for this question; products with all attribute options will be returned as matches.
   Pin Count       The pin count is the number of pins in the package. 
   Search Logic:      User may specify either, both, or neither of the "At Least" and "No More Than" values. Products returned as matches will meet all specified criteria.
   Number of Units in the Chip       The number of units is the chip is the number of flip-flops or latches in the chips.  
   Search Logic:      User may specify either, both, or neither of the "At Least" and "No More Than" values. Products returned as matches will meet all specified criteria.
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Features
           
   Your choices are...         
   Asynchronous Inputs       Devices with asynchronous inputs have preset and clear inputs. 
   Bus Hold Support       Circuits with bus hold support retain the bus's last active state when the bus is disabled or does not have an active driver.  
   Radiation Tolerant       Radiation-tolerant devices are hardened against radiation. 
   ESD Protection       Devices with electrostatic discharge (ESD) protection include circuitry that provides protection from electrostatic radiation. 
   Search Logic:      All products with ANY of the selected attributes will be returned as matches. Leaving all boxes unchecked will not limit the search criteria for this question; products with all attribute options will be returned as matches.
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