Parity Checkers and Generators Information

Show all Parity Checkers and Generators Manufacturers

Last revised: November 23, 2024

Reviewed by: Scott Orlosky, consulting engineer

Parity checkers and generators detect errors in binary data streams. Parity-checking devices combine a generator and checker into an integrated circuit (IC) package.

Parity

Parity is one of the simplest error-detection methods for checking binary data streams. Parity checkers contain transmission and receiving ends. They divide binary streams into sections of 7 or 8 bits and generate a parity bit at the transmission end. A second parity bit is then generated at the receiving end; if the transmission bit and receiving bit match, the data is verified as accurate.

Even/Odd Parity

Parity essentially measures the sum of the one bits (as opposed to zero, the other binary value) contained in the data and is classified as even or odd depending on these sums. With even parity, the sum of the ones plus the parity bit must be even, while in odd parity the sum must be odd. For example, if a device checks the data stream 0111000 for even parity, the parity bit must be 1 if the data is accurate; in this case the sum of the ones and parity bit is four, an even number.

The table below illustrates using parity bits to adjust data streams depending on whether parity is even or odd.

Image credit: University of London Birkbeck

Parity is a limited and somewhat simplistic method for checking binary data. It is prone to errors and shortcomings due to its status as a "pass-fail" sum-based method for error detection. For example, if a digit is switched during transmission parity can flag the data stream as "bad" but is unable to identify which bit caused the error.

Additionally, if two bits are switched, a parity checker would judge the data stream to be accurate because it can only gage whether the stream's sum of one digits is even or odd. Because adding two digits to any integer renders its parity identical, parity checkers are not reliable if two or four digits are switched in the same stream.

Applying Parity

Parity checkers are common in binary communications systems. They are also integrated into networked systems and computers, where they are used to test memory storage devices in real-time.

Errors and Causes

Parity errors may have "hard" or "soft" causes. Most errors are classified as soft errors, meaning they are caused by environmental factors such as electrostatic discharge (ESD) or electromagnetic interference (EMI). These conditions can unexpectedly change a memory cell's electrical state or interfere with its read/write functions. Soft errors typically occur only once and can be caused by nearby power cables, generators, lighting systems, and radiation issuing from solar flares or nuclear power systems.

Hard parity errors are caused by physical malfunctions in memory devices. A malformed memory cell may be unable to hold a charge or be more vulnerable to soft errors. Hard errors may also occur outside of healthy memory cells in the read/write circuity, causing a parity error in transmission. Because hard errors are due to physical anomalies, they recur each time the device is used. This error type is often caused by extreme temperatures, poor installation practices, ungrounded power surges, ESD, manufacturing errors, and component incompatibility.

Design and operation of a parity checker, showing the interaction between generation and check functions. Image credit: T4planet

Logic Families

A parity checker's logic family technology is one of its more important specifications. Some examples include:

Transistor-transistor logic (TTL) and related technologies such as Fairchild advanced Schottky TTL (FAST) use transistors as digital switches.
Emitter coupled logic (ECL) uses transistors to steer current through gates that compute logical functions.
Complementary metal-oxide semiconductor (CMOS) uses a combination of p-type and n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuit.
Bipolar CMOS (BiCMOS) is a silicon-germanium technology that combines the high speed of bipolar TTL with the low power consumption of CMOS.

Other logic families for parity checkers and generators include cross-bar switch technology (CBT), gallium arsenide (GaAs), integrated injection logic (I2L), silicon on sapphire (SOS), and gunning with transceiver logic (GTL).

Standards

Parity checkers may be designed and manufactured according to various published standards, including:

IETF RFC 5170—Low density parity check (LDPC) staircase and triangle forward error correction (FEC) schemes

Other parity-related standards can be found on Engineering360's standards page.

Parity Checkers and Generators FAQs

How are parity checkers integrated into digital communication systems?

Parity checkers are used to detect single-bit errors in data streams. They work by adding an additional parity bit to each data word, which represents the parity (even or odd) of the number of 1s in the word. During transmission, the parity checker recalculates the parity of the received data and compares it to the transmitted parity bit. If they do not match, an error is detected.

Parity checkers are commonly integrated into binary communication systems, networked systems, and computers. They are used to test memory storage devices in real-time, ensuring that data integrity is maintained during storage and retrieval processes.

While parity checkers are effective for detecting single-bit errors, they cannot detect multiple-bit errors, such as when two bits are switched. This limitation means that parity checkers are not foolproof and are often used in conjunction with other error detection and correction methods to enhance reliability.

How do parity checkers compare to other error detection methods?

When comparing parity checkers to other error detection methods, several key differences and considerations emerge:

Error Detection Capability

Parity Checkers: These are primarily designed to detect single-bit errors by adding a parity bit to data words.

Other Methods: More advanced error detection methods, such as checksums, cyclic redundancy checks (CRC), and error-correcting codes (ECC), can detect multiple-bit errors and, in some cases, correct them. These methods provide a higher level of data integrity assurance compared to parity checkers.

Complexity and Cost

Parity Checkers: They are relatively simple to implement and require minimal additional circuitry, making them cost-effective for basic error detection needs.

Other Methods: More sophisticated methods like CRC and ECC involve more complex algorithms and additional hardware, which can increase the cost and complexity of the system.

Correction Capability

Parity Checkers: They only detect errors and do not have the capability to correct them. This means that once an error is detected, additional mechanisms must be in place to handle the error, such as retransmission of data.

Other Methods: ECC, for example, not only detects errors but can also correct certain types of errors, providing a more robust solution for maintaining data integrity.

Use Cases

Parity Checkers: Suitable for applications where simplicity and low cost are priorities, and where the likelihood of multiple-bit errors is low. They are often used in memory storage devices and basic communication systems.

Other Methods: Preferred in environments where data integrity is critical, such as in network communications, data storage systems, and space applications, where the risk of multiple-bit errors is higher.

What are the differences between parity checkers and cyclic redundancy checks (CRC)?

Parity Checkers: These are designed to detect single-bit errors by adding a parity bit to data words. They are simple and cost-effective but have limitations in detecting multiple-bit errors. If two bits are switched, parity checkers may not detect the error because the overall parity remains unchanged.

Cyclic Redundancy Checks (CRC): CRCs are more advanced error detection methods that can detect multiple-bit errors. They use polynomial division to generate a checksum, which is appended to the data. The receiver performs the same division and compares the result to the checksum to detect errors. CRCs provide a higher level of data integrity assurance compared to parity checkers.

Parity Checkers: They are relatively simple to implement and require minimal additional circuitry, making them cost-effective for basic error detection needs

CRCs: These involve more complex algorithms and additional hardware, which can increase the cost and complexity of the system. However, they offer more robust error detection capabilities.

CRCs: Like parity checkers, CRCs are primarily used for error detection and do not inherently provide error correction. However, they are often used in conjunction with error-correcting codes (ECC) for more comprehensive error management.

CRCs: Preferred in environments where data integrity is critical, such as in network communications, data storage systems, and space applications, where the risk of multiple-bit errors is higher.

What is the difference between block codes and convolutional codes in error-correcting codes (ECC)?

Structure and Encoding

Block Codes: These codes operate on fixed-size blocks of data. Each block of input bits is encoded into a block of output bits. The encoding process is straightforward and does not depend on previous blocks. Block codes are typically represented by the notation ([n, k, t]), where (n) is the total number of bits in the encoded block, (k) is the number of input bits, and (t) is the number of errors that can be corrected.

Convolutional Codes: These codes process data as a continuous stream rather than in fixed-size blocks. The encoding involves memory, meaning the output depends on the current input and a few previous inputs. This introduces a memory effect, characterized by the constraint length, which is the number of previous input bits that affect the current output.

Error Correction Capability

Block Codes: They are well-suited for correcting random errors within a block. Examples include Hamming codes and Reed-Solomon codes, which are effective for correcting burst errors in applications like digital audio and video.

Convolutional Codes: These are particularly effective in correcting errors in a continuous data stream and are often used in conjunction with algorithms like the Viterbi algorithm for decoding. They are widely used in applications where data is transmitted over noisy channels, such as in space communications.

Complexity and Implementation

Block Codes: Generally simpler to implement, as they do not require memory and the encoding/decoding processes are straightforward. They are often used in systems where simplicity and low latency are important.

Convolutional Codes: More complex due to the memory requirement and the need for sophisticated decoding algorithms like the Viterbi algorithm. However, they offer better performance in terms of error correction in certain conditions, such as channels with burst errors.

Applications

Block Codes: Commonly used in data storage systems, digital communication systems, and applications where data is processed in discrete blocks.

Convolutional Codes: Widely used in real-time communication systems, such as satellite and mobile communications, where data is transmitted continuously.

What are the differences between parity checkers and error-correcting codes (ECC)?

Error Detection vs. Error Correction

Parity Checkers: These are primarily designed for error detection. They add a parity bit to data words to detect single-bit errors. If the parity of the received data does not match the parity bit, an error is detected, but there is no mechanism for direct correction.

Error-Correcting Codes (ECC): ECCs are designed to both detect and correct errors. They add redundancy to the data, allowing the receiver to identify and correct certain types of errors without needing retransmission. This makes ECCs more robust in maintaining data integrity compared to parity checkers.

Complexity and Implementation

Parity Checkers: They are relatively simple to implement and require minimal additional circuitry, making them cost-effective for basic error detection needs.

ECC: These involve more complex algorithms and additional hardware, which can increase the cost and complexity of the system. ECCs, such as block codes and convolutional codes, require sophisticated encoding and decoding processes but offer better performance in terms of error correction.

Use Cases

Parity Checkers: Suitable for applications where simplicity and low cost are priorities, and where the likelihood of multiple-bit errors is low i.e. memory storage.

ECC: Preferred in environments where data integrity is critical, and the risk of multiple bits is higher. Examples would be real-time communication systems, such as satellite and mobile communications.