TABLE OF CONTENTS MICHAEL P. FLYNN, SUNGHYUN PARK, AND CHUN C. LEE
Electrical Engineering & Computer Science, University of Michigan, 1301 Beal Avenue,
Ann Arbor, Michigan 48109-2122, USA
mpflynn@eecs.umich.edu
This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer r gime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that V T matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to finer processes. It has long been known that thermal noise causes the power consumption of analog circuits to increase with scaling. However, unlike the case with thermal noise, new circuit techniques can break the accuracy-power constraints related to mismatch. These techniques are based on analog circuit redundancy, and take advantage of the tremendous transistor density offered by nanometer CMOS. This paper is primarily concerned with comparators, and in particular, with the use of comparators in flash ADCs; however, the analysis is also applicable to other circuits and applications.
| Keywords: | Analog circuits, CMOS, mismatch, offset, flash, ADC, offset cancellation. |
The performance of analog circuits depends on both the absolute value of component parameters, such as resistance, capacitance, and transconductance, and the matching of the parameter values for different components. Absolute...
