Design of High-Speed Communication Circuits

Designing LC VCOs Using Capacitive Degeneration Techniques

Byunghoo Jung and Ramesh Harjani
Department of Electrical and Computer Engineering, University of Minnesota, 200 Union Street S.E. Minneapolis, Minnesota 55455, USA
harjani@ece. umn. edu

Overview

In this paper, we present a detailed analysis of VCOs using a capacitively degenerated negative resistance cell. The negative resistance cell using capacitive degeneration has a higher maximum attainable oscillation frequency and a smaller equivalent shunt capacitance when compared to the widely used cross-coupled negative- g m cell. These properties are of particular interest for the design of high-frequency and/or wide tuning range VCOs. The negative resistance provided by a traditional capacitively degenerated negative resistance cell is lower than that provided by a cross-coupled negative- g m cell. We present an active capacitive degeneration topology that overcomes this limitation. To validate this circuit topology we use two test vehicles. The first test vehicle is a 5.3 GHz VCO designed in a 0.25 ?m CMOS technology and the second test vehicle is a 20 GHz VCO designed in a 0.25 ?m BiCMOS technology. Measurement and simulation results from both test vehicles effectively demonstrate the efficacy of the capacitive degeneration technique.

Keywords: Voltage-controlled oscillators; analog integrated circuits; BiCMOS integrated circuits; capacitive degeneration; high-frequency LC oscillators; negative resistance cell.

[1]Portions of this manuscript and material referred in this manuscript have appeared in [18], [19], and [20].

1. Introduction

Integrated LC voltage-controlled oscillators (VCOs) are critical building blocks in high-performance communication systems. The ever-increasing demand for bandwidth places very...

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