Overview

In this tutorial paper we present equalization techniques to mitigate inter-symbol interference (ISI) in high-speed communication links. Both transmit and receive equalizers are analyzed and high-speed circuits implementing them are presented. It is shown that a digital transmit equalizer is the simplest to design, while a continuous-time receive equalizer generally provides better performance. Decision feedback equalizer (DFE) is described and the loop latency problem is addressed. Finally, techniques to set the equalizer parameters adaptively are presented.

Keywords: Serial Link; Eye Diagram; ISI; Equalizer; Jitter; BER; Transceiver; Noise; DFE; Pre-emphasis.

1. Introduction

Recent advances in integrated circuit (IC) fabrication technology coupled with innovative circuit and architectural techniques led to the design of high performance digital systems. The complex systems are built by combining several ICs consisting of millions of transistors operating at multi-gigahertz frequency. These systems require efficient communication between multiple chips for proper functioning of the whole system. However, the off-chip bandwidth scales1 at a much lower rate compared to the on-chip bandwidth,2 thus making the communication link (also referred to as serial link) between chips the major bottleneck for the overall performance. For example, present day microprocessors run at several gigahertz clock rates, while...