Digital Clocks for Synchronization and Communications
This text explains important phase-lock circuit design techniques, and how to select commercially available equipment for a variety of projects in the field.
TABLE OF CONTENTS Digital Clocks for Synchronization and Communications
Chapter 5: PLL Characteristic Analysis
5.1 Basic Analysis of PLL Characteristics
A clarified relationship between the input and output signals of a PLL is needed in order to analyze its characteristics quantitatively and in detail. This section describes the frequency and phase control mechanisms of a PLL, examines how it synchronizes to the input signal, and discusses the synchronization accuracy.
5.1.1 Issues Related to the Output Frequency
An understanding of the mechanism that determines the PLL output frequency is vital for elucidating its characteristics. The output frequency depends on the free-running frequency of the controlled oscillator and the frequency offset created by PLL operation, as shown in Figure 5.1. The free-running frequency is the frequency that is output by the controlled oscillator if no control signal is given to it. Although this frequency can be expected to be within a certain range, it is not guaranteed to equal the input frequency. It has to be corrected in a phase synchronization process. The frequency offset corresponds to the difference between the input frequency and the free-running frequency, and fit is output by the feedback circuit of the PLL. The frequency offset enables the output frequency of the PLL to be controlled in the phase synchronization process. The output frequency f o( t) is expressed as the sum of the free-running frequency f free( t) and the frequency offset ? f contv( t) that results from PLL control, as shown in (5.1).
Figure 5.1: Output frequency decision mechanism.
In the analog...
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