Digital Clocks for Synchronization and Communications
This text explains important phase-lock circuit design techniques, and how to select commercially available equipment for a variety of projects in the field.
TABLE OF CONTENTS Digital Clocks for Synchronization and Communications
Chapter 11: DDS Circuit Configuration and Characteristics
DDS allows us to build synthesizers that can generate variable and multiple frequencies and arbitrary waveforms as mentioned in Chapter 10. Theoretically all signals can be generated by the DDS concept only limited by the circuit processing speed and the sampling theorem. However, practical circuit configurations and design parameters determine the DDS output frequency and signal characteristics. In particular, output signal purity should be considered sufficiently. Undesired frequency components are inevitable in digital processing and they degrade signal purity. This chapter describes the relationships between DDS circuit configurations and their output characteristics such as the spurious generation mechanism.
11.1 Basic Parameters
11.1.1 Output Frequency
The DDS output is determined by the digital data generated by the processing part based on a system clock. According to Shannon's sampling theorem, the maximum output frequency of the DDS cannot exceed 50% of the system clock, but the practical limit is empirically supposed to be around 33% of the system clock or even lower. Here, the spurious characteristics in the output are a major concern.
Figure 11.1 shows the circuit that directly uses the output of the processing part to generate the sawtooth waveform shown in Figure 11.2(a). The output is accumulated by the adder over each clock and is reset when the accumulated value reaches the maximum of the adder. The phase accumulation speed for one clock is determined by the phase increment ? i of the adder input. Assuming a 4-bit adder and phase register and a phase increment value of 3,...
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