Digital Clocks for Synchronization and Communications

This chapter deals with the necessary design methods for the network synchronization clock system described in Section 7.1.3. A digital PLL is selected as a design example, since it is often used in a practical clock system. Design parameters of various digital PLL elements (a digital-processing phase comparator, a digital-controlled oscillator, and an active integrating digital filter) are explained. The total PLL characteristics that vary with those parameters are described as well.
The most important component of a PLL is the controlled oscillator. PLL performance can be improved to some extent by optimizing its design parameters and by using additional circuits such as a variable time constant circuit and a high-order filter. The improvements that are possible with these techniques, however, pale in comparison with those achieved by using a highly stable oscillator. A fundamental requirement is a controlled oscillator with good frequency stability. Oscillator selection requires us to balance performance, cost, and size. The size and cost often dominate the selection process. If the maximum size and cost are given, the upper stability limit and hence overall PLL performance can be approximated. Generally speaking, the smaller an oscillator is, the worse its frequency stability is. In a controlled oscillator with poor stability, the output frequency can exceed the specified value if the frequency control is slow compared to the frequency variation of the oscillator itself. The best solution is to set the PLL cutoff frequency high whereby the control loop time constant gets shorter. This improves the frequency...