Digital Integrated Circuit Design
Working from the fundamentals of transistor-level design and building up to system-level considerations, this text demonstrates how to design state-of-the-art high performance digital integrated circuits.
TABLE OF CONTENTS Digital Integrated Circuit Design
3.4: Advanced MOS Modeling
3.4 Advanced MOS Modeling
In this section, we look at some of the more advanced modeling concepts that a microcircuit designer is likely to encounter scaling, short-channel effects, subthreshold operation, leakage currents, and latch-up.
SCALING
When a technology is scaled to smaller dimensions, one would like to keep the device operation unchanged, except for taking advantage of the higher speed available. This is possible, ideally, if the scaling is done to keep a constant electric field. This is theoretically possible if the voltage levels are scaled proportional to the device dimensions and the doping levels are scaled inversely proportional to device dimensions. Thus, if the topography dimensions are scaled down by a factor 1 / S where S > 1, then for constant-field scaling one needs voltages scaled by 1 / S and doping levels scaled by S. This constant-field scaling ideally leaves all carrier velocities unchanged. It is easy to calculate its effect on many other important characteristics of digital ICs.
For example, repeating equation (3.60), we have
Since d ox is inversely proportional to S, we have the gate capacitance per unit area, C ox, increasing proportionately to S. But since the gate area goes down inversely proportional to S 2, we have the total gate capacitance scaling proportional to 1 / S.
Also, from equations (3.69) and (3.71), we see that the drain currents of MOS transistors are proportional to C ox and also...
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