6.1 Delay of MOS Circuits

As we have seen previously, the transient delay of a CMOS inverter is often approximated using an RC approximation. Similarly, when analyzing more complicated gates for their transient responses, the gates are modeled using RC circuits. Often, the resulting RC circuit will be a ladder structure with resistors interconnected between nodes and capacitors connected between nodes and ground. The resistor values are found using the approximately equivalent resistor concept presented in Section 4.1. The calculation of the parasitic capacitances has been previously discussed, but will be described in more detail in this chapter.

As has been mentioned, there are typically three different components that are primarily responsible for the parasitic and load capacitances of MOS circuits. These are gate capacitances, junction capacitances, and interconnect capacitances. Each will be discussed in turn. Much of this section is repeated from the section on layout from Chapter 3.

GATE CAPACITANCES

The transistor gate capacitances often dominate in situations in which only a number of close logic gates are being driven. Typical examples of this include arithmetic circuits such as adders, multipliers, controllers, and arithmetic logic units in microprocessors.

The exact calculation of the capacitances due to gate connections is complicated and highly nonlinear; a transistor's gate capacitance changes substantially depending on the node voltages of the transistor. For example, if the gate has a channel present and is in the active region, its gate capacitance is approximately given by

The first term is the intrinsic gate capacitance,...