Digital Integrated Circuit Design
Working from the fundamentals of transistor-level design and building up to system-level considerations, this text demonstrates how to design state-of-the-art high performance digital integrated circuits.
TABLE OF CONTENTS Digital Integrated Circuit Design
Chapter 9: Advanced CMOS Logic Design
Up to this point, we have seen a number of techniques for realizing digital integrated logic circuits using both MOS and bipolar technologies. This chapter will describe many of the advanced logic design techniques that have become popular recently for state-of-the-art CMOS ICs. These techniques have been developed in response to the never-ending goal of increasing speed while minimizing silicon area and power dissipation. Most, but not all, of these techniques involve dynamic circuits of one type or another. Some of the techniques have already been introduced as examples, but, in many cases, they will be described again for completeness. As always, rather than trying to present a review of all of the design techniques that have been used, the principles involved will be emphasized with some of the more important techniques used as examples.
9.1 Pseudo-NMOS and Dynamic Precharging
As has been seen, traditional CMOS logic design normally requires as many p-channel transistors as n-channel transistors. This requires considerable area, particularly if the p-channel transistors are chosen to be wider than the n-channel transistors. In addition, due to the lower mobility of the p-channel transistors, the "0" to "1" transition of the logic gates may be slow if there are a number of series p-channel transistors between the output and the positive power supply. In response to these problems, modern CMOS design strives to minimize the number of p-channel transistors, particularly series p-channel transistors. Not only does this save on area,...
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