Digital Integrated Circuit Design
Working from the fundamentals of transistor-level design and building up to system-level considerations, this text demonstrates how to design state-of-the-art high performance digital integrated circuits.
TABLE OF CONTENTS Digital Integrated Circuit Design
Chapter 10: Digital Integrated System Building Blocks
This chapter describes a number of digital integrated system building blocks. It is not intended to be all encompassing; rather, it is intended to give the reader exposure to a number of different circuits and methodologies. Some of the circuits described include multiplexors, decoders, barrel shifters, counters, adders, subtractors, multipliers, and programmable logic arrays.
10.1 Multiplexors and Decoders
A multiplexor is a circuit that makes the output equal to one of a number of possible data inputs as determined by address inputs. An example of a multiplexor was seen previously in Fig. 5.5 of Chapter 5, where n-channel transmission gates were used to realize an 8-to-1 multiplexor. Alternatively, this could be realized using CMOS transmission gates. Another alternative example of a multiplexor is shown in Fig. 10.1. This structure is somewhat similar to the transmission-gate multiplexor, except now the tree is only used to pull internal nodes low and a pseudo-NMOS load is used to pull internal nodes high. Alternatively, the pseudo-NMOS load could be replaced by a dynamic load. The multiplexor also has an output inverter that also serves the purpose as a buffer. If all the n-channel transistors in the inverted-tree network are taken as 10 ?m wide, then a reasonable width for the pseudo-NMOS load might be 5 ?m. This assumes all lengths are equal and taken as the minimum allowed.
Figure 10.1: An inverted-tree multiplexor.
A fourth alternative circuit for realizing an...
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