Introduction to PCI Express: A Hardware and Software Developer's Guide

Chapter 7: Data Link Layer Architecture

Overview

An error the breadth of a single hair can lead one a thousand miles astray.

Chinese Proverb

This chapter describes the details of the middle PCI Express architectural layer, the Data Link Layer. The Data Link Layer s main responsibility is error detection and correction as well as link management support. The chapter discusses the sequence number and LCRC (Link CRC), and how they are added to the Transaction Layer Packet (TLP) to ensure data integrity. It then describes the functions specific to the Data Link Layer, particularly the creation and consumption of Data Link Layer Packets (DLLPs).

Data Link Layer Overview

The Data Link Layer serves as the gatekeeper for each individual link within a PCI Express system. It ensures that the data being sent back and forth across the link is correct and received in the same order it was sent. The Data Link Layer makes sure that each packet makes it across the link, and makes it across intact.

This layer takes TLPs from the transmit side of the Transaction Layer and continues the process of building them into a PCI Express transaction. The Data Link Layer adds a sequence number to the front of the packet and an LCRC error checker to the tail. Once the transmit side of the Data Link Layer has applied these to the TLP, the Data Link Layer forwards it on to the Physical Layer. Like the Transaction Layer, the Data Link Layer has unique duties for both outgoing packets and...

UNLIMITED FREE
ACCESS
TO THE WORLD'S BEST IDEAS

SUBMIT
Already a GlobalSpec user? Log in.

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.

Customize Your GlobalSpec Experience

Category: RapidIO Products
Finish!
Privacy Policy

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.