The Physical Layer of PCI Express is the engine that will power next generation busses to frequencies that exceed the transmission capabilities (10 gigahertz) of copper wire. The objective of this section is not to explore what mediums will be used once the bandwidth limits of copper wire have been reached; however, to satisfy curiosity it can be noted that optical wires are a likely solution.

The Physical Layer contains all the necessary digital and analog circuits required to configure and maintain a link. Additionally, the Physical Layer may contain a phase locked loop (PLL) to provide the necessary clocking to drive the serial shift registers of the transmitter output stages. Given the understanding that PCI Express may support data rates greater than 2.5 gigabits per second, the data rate detect mechanisms have been predefined to minimize the changes required to support future generations of PCI Express. Additionally, the layers of PCI Express are organized to provide isolation of the circuits and logic that need to be modified and/or tuned in order to support next generation speeds. As an example, the Physical Layer is a separate entity from the Data Link and Transaction Layers, as illustrated in Figure 8.1. Next generation frequency changes will only require changing the Physical Layer. This eases the transition of upgrading the technology by allowing maximum reuse of the upper layers.

Figure 8.1: Physical Layer Positioning

There are two key sub-blocks that make up the Physical Layer architecture: a logical sub-block and...