TABLE OF CONTENTS Our Age of Anxiety is, in great part, the result of trying to do today's jobs with yesterday's tools.
Marshall McLuhan
This chapter touches on some of the basics for PCI Express implementation. It begins with some examples of chipset partitioning, explaining how PCI Express could be used in desktop, mobile, or server environments. The rest of the chapter identifies some of the ways that PCI Express lives within, or can expand, today s computer systems. This focuses on example connectors and add-in cards, revolutionary form factors, and system level implementation details such as routing constraints.
PCI Express provides a great amount of flexibility in the ways that it can be used within a system. Rather than try to explain all the various ways that this architecture could be used, this section focuses on how the chipset may implement a PCI Express topology. Generically speaking, the chipset is the way that the CPU talks to the rest of the components within a system. It connects the CPU with memory, graphics, I/O components, and storage. A common chipset division is to have a (G)MCH and an ICH. The GMCH (Graphics & Memory Controller Hub) connects the CPU to system memory, graphics (optionally), and to the ICH. The ICH (I/O Controller Hub), then branches out to communicate with generic I/O devices, storage, and so on.
How exactly could a chipset like this make use of PCI Express? First, recall the generic PCI Express topology discussed in Chapter 5 and shown...
