Introduction to PCI Express: A Hardware and Software Developer's Guide

Those parts of the system that you can hit with a hammer are called hardware; those program instructions that you can only curse at are called software.
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This chapter introduces the PCI Express software architecture. It starts off with an explanation of device and system configuration. This addresses the basics of how PCI Express devices can live within the existing PCI configuration environment, as well as how PCI Express allows for additional configuration capabilities. Next, the chapter goes into the baseline and advanced error reporting capabilities offered by the architecture. Finally, the chapter contains a discussion of how the software architecture supports some of the newer features, such as power management, hot plug, and isochrony.
The PCI Express Base Specification defines two models for configuration space access. The first is a PCI-compatible configuration mechanism that supports 100 percent binary compatibility with operating systems that support the PCI Local Bus Specification, Revision 2.3 configuration model. Support for this model should ease the adoption of PCI Express because it removes the dependency on operating system support for PCI Express to have baseline functionality. The second PCI Express configuration model is referred to as the enhanced mechanism. The enhanced mechanism increases the size of available configuration space and provides some optimizations for access to that space.
To maintain compatibility with the existing PCI software configuration mechanisms, all PCI Express devices have a PCI compatible configuration space representation. Recall that all PCI device functions...