TABLE OF CONTENTS Recall from Chapter 3 that a lane is a set of differential transmit and receive pairs and that a link is a collection of lanes forming a dual unidirectional communication between two PCI Express devices. The link and lane training process is a coordinated effort between the logical and the electrical sub-blocks. These sub-blocks work together to configure individual lanes into a functioning link. Training the link requires an understanding of the link data rate, lane ordering and link width, lane-to-lane skew, and lane polarity. There are seven link training states, the detect, polling, configuration, disable, recovery, hot reset, and loopback states, as shown in Figure 8.11. The following discussion focuses on the details associated with the detect, polling, and configuration link training states, which are considered the primary states used during the training process. The other training states are touched upon briefly.
Before describing the link configuration states it seems appropriate to define electrical idle since it will be referred to throughout the remainder of this chapter. The electrical idle state is a steady state condition where the Transmit pairs TX+ and TX- are held at a constant value. The PCI Express Base Specification defines constant as meaning that the differential pair lines have no more than 20 millivolts of difference between the pair after factoring out any DC common element. The minimum time that a transmitter must remain in electrical idle is 20 nanoseconds, however,...
