TABLE OF CONTENTS PCI Express has several power management states that can either be driven by the request of software or are actively managed by the Physical Layer. This section focuses on the actively managed link power states controlled by the Physical Layer. For additional power management details not covered here, refer to Chapter 11.
The PCI Express Base Specification defines two Active State Power Management states to lower the power consumption of the link. The first state is called L0s. According to the PCI Express Base Specification this state must be supported. The second Active State Power Management state is the L1 state. Support for this state is optional. Software enables the use of these states. However, the Physical Layer actually handles the autonomous function of managing the power states. By default, PCI Express devices power up with this functionality turned off.
When the L0s state is enabled, the Physical Layer transitions the link to this state whenever the link is not in use, as shown in Figure 8.11. This power-saving state is managed on a per-direction basis. In other words, the transmit path from the upstream device could be in the L0s state while the receive path to the upstream device could remain in the fully functional L0 state. Because the link transitions into and out of this state often, the latencies associated with coming in and out of this state must be relatively small (a maximum of several microseconds). During this state...
