TABLE OF CONTENTS Feature sizes decreasing to the nanometer range, the increasing need for low defect densities, increasing chip density and size, along with larger diameter wafers have challenged the industry to squeeze every capability out of traditional processes and develop new ones. The problems encountered and current solutions to reaching nanometer circuit dimensions are explored in this chapter. Included is a discussion of post-optical lithography techniques, collectively known as next-generation lithography (NGL).
Upon completion of this chapter, you should be able to:
Describe four exposure-related effects that cause image distortion.
Draw a cross-sectional flow diagram of a dual-layer resist process.
Draw a cross-section flow diagram of a dual damascene process.
List two planarization techniques.
State an advantage of an image-reversal process.
Describe how antireflective layers, contrast enhancement layers, and resist dye additives improve resolution.
Identify the parts of a pellicle and the advantages it offers to a resist process.
The ten-step patterning process detailed in Chapters 8 and 9 is a one-photoresist-layer basic process. It would be sufficient for the production of MSI and some simple LSI and VLSI circuits. However, the VLSI/ULSI demands of decreasing feature sizes and defect densities is beyond the capabilities of the basic process. The limits showed up at the sub-three (3) micron level and became critical in the submicron era. Problems include physical limitations associated with the optical exposure equipment, resolution limits of photoresists, and a host of surface problems, including reflective...
