During the years, a number of layout concepts have been in use [1], but the interdigitated cell layout in Figure 4 dominates cellular applications today For the common-emitter configuration, this layout offers the best performance with respect to RF gain, power/current distribution and area utilization.

Figure 4: Interdigitated cell layout for RF power transistor.

The most critical parasitic capacitance for the gain is between collector and base. In a vertical RF power transistor, the silicon substrate is connected to the collector. The device area consists of a single diffused base tub, the area of which must be minimized for a given power requirement to obtain best possible gain.

The base metal also contributes to collector-base capacitance; therefore, the layout dimensions are as narrow as possible. The emitter metal area, which must feed high currents, has been tapered toward the ends of the cell to save some additional collector-emitter capacitance.

The bond pads do not have square form; instead they are rectangular, similar to the foot-print of the bonding wire. To further reduce capacitance, the pad corners have been rounded.

The collector is connected to the backside of the chip, i.e., only two types of bond pads, emitter and base, need to be bonded using wires. By dividing larger cells into smaller units and spreading them over the silicon surface, the total thermal resistance can be lowered, but at the cost of increased interconnect metallization capacitance. In practice, the thermal improvements are moderate...