TABLE OF CONTENTS The Link layer protocol forms the basis of coordinated communication and control between a host and device. Chapter 9 outlined the encoding/decoding of the characters transmitted over the interface; this chapter describes the sequence of such characters that are exchanged and the low-level coordination between a transmitter and receiver used to deliver information reliably. In this chapter we will cover:
Link primitives and basic services
Scrambling to reduce EMI while idle
Scrambling to reduce EMI while delivering data
Cyclic Redundancy Check (CRC)
The Idle state machine
The Transmit protocol state machine
The Receive protocol state machine
The Power management state machine
Figure 10.1 indicates the layers of the architecture that are covered in this chapter.
The Link layer is responsible for coordination and control between host and device and for delivering packets of payload data. The payload data packets are referred to as frame information structures (FISes). The FISes and their function are defined in Chapter 11, Transport Layer Frames and Data Structures.
The Link layer protocol relies on the dual unidirectional communication scheme that is used in Serial ATA for maintaining coordination between a transmitter and receiver. Therefore, both the host and device have transmit and receive traffic occurring simultaneously. Although this could imply that data could be delivered simultaneously in both directions, the protocol actually restricts delivery of payload data to one direction at a time only, with no provision for the host to transmit payload...
