Overview

The Transport layer protocol defines the sequences of FISes that can be transmitted across the interface. Because the Link layer handles everything involved in reliably delivering a FIS, the Transport layer need not be concerned with the details involved in delivering FISes or with checking them for integrity. While the previous chapter described the format and function of all the data structures related to the Transport layer, this chapter describes the protocol that defines the legal sequences in which such data structures can be exchanged. Figure 12.1 indicates the layer of the architecture covered in this chapter.

Figure 12.1: The Transport Layer in the Serial ATA Layered Architecture

Much of the Transport layer protocol is somewhat uninteresting, as the majority of transactions over the Serial ATA interface involve the transmission of a single FIS. In a few instances, however, a sequence of FISes must be issued in a particular sequence if they are to yield valid transactions. It is those few scenarios that require particular FIS sequences that warrant a little extra discussion.

Host State Machine

The Serial ATA specification separates the host and device Transport layer state machines since the protocol is not entirely symmetric. The host state machine describes the behavior of the host controller in transmitting and receiving the FIS data structures defined in the previous chapter.