Processor Design: System-On-Chip Computing for ASICs and FPGAs

Since the earliest days of computing, there have been repeated efforts to drive the programming problem up in abstraction level from patch-board programming, to toggle-switch entry, to machine-language entry, to assembly language, and then to a whole host of high-level programming languages (HLLs) starting with Fortran and COBOL in the 1950s and working through hundreds or thousands of programming languages over the next half century.
As soon as HLLs were developed, people began worrying about the semantic gap between HLL descriptions used to capture solutions to programming problems and the actual instructions generated by the HLL compiler to be executed on a target machine. Early compilers often produced poor results sometimes very poor. Even today, despite more than five decades of compiler development, the quality of results that can be achieved for many algorithms by the most highly skilled human assembly-language coders can be an order of magnitude better (or more) than code produced by the best HLL programmers combined with the best available optimizing compilers.
Inevitably, computer researchers and commercial computer vendors began to investigate the feasibility of tuning a particular processor to specific HLLs or language classes in an attempt to more closely match the processor s instruction set with the language s requirements and narrow the semantic gap. The theory was that programs written in those targeted HLLs would execute much more efficiently on these tuned machines.
Many decades...