Introduction

We are hitting power budget and power density limitations ever harder with continuing electronics miniaturization. High power density is not a new problem: CMOS technologies were adopted in the late 70s and early 80s mainly because of their lower power density in comparison to bipolar processes. This time there is no such alternative, more energy efficient technology at sight. Thus, the solution lies in methodological and architectural innovation for more efficient energy utilization. Intel s Senior Vice President and CTO, Patrick P. Gelsinger, has noted that for every doubling of available transistors, we have gained approximately 40% in design performance. This observation suggests that performance per transistor, and hence energy efficiency, has degraded significantly.

Desktop computers deliver a high performance by means of instruction-level parallel (ILP) processing. Efficient implementation of ILP processors requires speculative processing and instruction reordering to maintain program consistency. This requires a considerable amount of supporting logic. The supporting logic itself consumes a lot of energy. The problem is compounded by discarded branches that were processed speculatively. The result is power density that exceeds physical limits of heat sinking and thus limits performance.

Portable devices incorporate multiple processors for different functions. Current CMOS processes feature a low switching energy for the transistors, but high energy utilization in the wires. Thus, even if the processors are located on the same silicon die there is a severe...