Overview

The emergence of Systems-on-Chip (SoC) has generated a tremendous development in application demands. Continuous algorithmic innovation imposes the need for flexibility, intended as the capability of a given processing engine to adapt to new computation patterns after fabrication. In spite of the boost offered by sheer technology development, programmable architectures can hardly meet requirements. The conventional solution of gaining performance through application-specific circuits is severely affected by design and verification costs, and the concurrent shortening of time-to-market. Design-time programmable processors provide a solution only valid for those products that can afford the cost of providing a new set of masks for each upgrade of the target application field.

The term run-time Reconfigurable Processor (RP) indicates a processor architecture that takes advantage of some form of run-time (dynamically) configurable hardware to provide adaptive instruction set modification, in order to meet application requirements. Such processors hold the promise to couple software flexibility with performance comparable to application-specific hardware. Many open issues remain especially related to the programming environment and the ideal dimensioning of the configurable hardware segments. This section provides an overview of the state of the art in the field. Starting from the formalization of the instruction set metamorphosis concept, it describes its evolution in the research environment up to these days and the first commercial offers that are appearing on the market, underlining classical advantages and main architectural options related to RP design and...