TABLE OF CONTENTS The designers of the IBM 7030 (Stretch) computer were the first to use processor pipelining, back in 1961. They used this technique to raise the processor s clock rate by restricting the amount of logic operating within each pipeline stage during each clock period thus cutting the transit time through each stage. Because latches isolate each pipeline stage, each stage works on a different instruction during each clock period, which increases parallelism and therefore increases an important figure of merit for processors: IPC.
Pipelining became popular in microprocessor design with the advent of RISC processors, which standardized on 5-stage pipelines early on. A classical, 5-stage pipelined RISC processor might have the following pipeline stages:
IF Instruction fetch (usually from instruction cache or local memory)
RD Read the source operands from the register file
ALU Perform the operation specified by the instruction
MEM Read memory (for a load) or write to memory (for a store)
WB Write back, write operation result to the register file
Each of these stages performs a complete and well-defined task. However, it s possible to make pipelining work even faster by dividing each task into subtasks and each stage into sub stages, which further reduces the amount of logic within each stage and thus boosts maximum clock rates to ever more stratospheric heights. However, this approach also increases the number of clocks needed to complete the execution of each instruction. The...
