Processor Design: System-On-Chip Computing for ASICs and FPGAs

Seppo Virtanen 1 , Dragos Truscan 2 , Sanna M tt 3 , Tomi Westerlund 1 ,
Jouni Isoaho 1 , and Jari Nurmi 3
University of Turku 1
bo Akademi University 2
Tampere University of Technology 3
Due to the increasing complexity of system specifications, new methods are required for detecting design errors at the early stages of the development process, as well as for ensuring the performance characteristics of the final product. Among these are estimation of physical characteristics (discussed in the previous chapter, Early Estimation Modeling of Processors) and system simulation at a high abstraction level, that is, the system level as defined in [344]. High abstraction level estimation and simulation have both become necessities for the design activity. System level simulation enables the evaluation of system specifications against requirements at early stages of the development, before proceeding to hardware implementation. The approach eliminates costs and shortens the design cycle of new products. According to [294], most of the integrated circuits developed today require at least one return to early phases of the development, due to errors. Furthermore, simulation contributes to reducing the testing effort that is performed at different stages of the design process.
Simulation allows one to execute the system specification at different levels of abstraction. There are two conflicting trends in simulating embedded systems. On the one hand, the simulation process should be performed as early in the development process as possible, in order to avoid the propagation of design errors to later...