Introduction

The clock is a periodic synchronization signal used as a time reference for data transfers in synchronous digital systems. Since the clock plays a central role in the operation of a synchronous system, significant effort is invested in the design, optimization and verification of high-performance clock distribution schemes. Because the clock edges determine the state updates in a synchronous system, higher clock frequencies are generally (but not always) associated with a higher system performance. Clock frequency for mainstream microprocessors has increased significantly over time, driven by the process technology scaling, aggressive circuit design techniques and deeper pipelines.

The clock distribution is particularly affected by process scaling. Smaller process geometries allow designers to pack more functionality on a single die. The number of sequential elements that need the clock is constantly increasing, thus making the clock distribution a more difficult task. Transistors are getting smaller and faster, so clock deskew or compensation circuits are cheaper to design. However, the metal interconnect does not scale well and that requires careful extraction and modeling of the clock tree lines resistance and capacitance. This trend is aggravated by the increase in die size since the clock needs to be distributed to all the sequential circuits on the die, therefore the clock lines are getting longer and require more buffering levels. For high frequency clocks (generally above 1 GHz) the inductive effects in the clock distribution lines must also be modeled.

This chapter is organized as follows: A section on...