Overview

Claudio Mucci ¹ , Fabio Campi ² , Claudio Brunelli ³ , and Jari Nurmi ³

ARCES ¹ , University of Bologna ¹

STMicroelectronics ²

Tampere University of Technology ³

The capability to tailor processor instruction set architecture (ISA) around the computational requirements of a given application is proposed today as the most appealing way to match performance with very short time-to-market, thus reduction non-recurring engineering (NRE) costs. From Mask-Time Configurable Processors (MTCPs) to Run-Time Reconfigurable Processors (RTRPs), ISA customization is performed transferring the implementation of critical kernels from software to hardware. This introduces a new design-space exploration problem that requires skills in both software and hardware design. Since adaptive processors appear as the natural extension of Digital Signal Processors (DSPs), programming tools for customizable processors need to be as similar as possible to standard software development environments, in order to enable the adaptive computing to the wide audience of DSP programmers. While fast design-space exploration can be performed using high-level description languages, programmers proficient in hardware design can further improve performance through structural descriptions involving, for example, the direct utilization of macro-operators or the possibility of balancing critical paths through register insertion. The widespread knowledge of ANSI C among developers suggests its usage as main entry language for both configurable and reconfigurable architectures. This in turn introduces the problem of translating C codes (or C dialects) into some kind of hardware description, be it HDL in case of MTCPs or bit-stream for RTRPs. In this context, data-flow graphs...