TABLE OF CONTENTS Manuel Jes s Bellido D az David Guerrero Martos
In logic timing simulation, a delay model is used to predict the dynamic behaviour of every element of the circuit (transistor net in transistor level simulation, logic gates in gate level simulation). The simulation precision depends on the precision of the delay model used.
Delay models can be classified into two categories: deterministic and non-deterministic. These categories have several subtypes (Table 2.1) which will be presented in this chapter.
| Deterministic Calculate a specific value for the propagation delay. | Zero delay Outputs change instantaneously when inputs change. Only functional simulation is carried out. |
| Unitary delay The delay value is the same and fixed for every circuit component. The timing information obtained is qualitative. | |
| Assignable delay Delay has a separate value for each circuit component. | Static The delay depends on the circuit and parameters that do not change with time. The results are quite accurate under bounded operating conditions. |
| Dynamic The delay depends on the waveform as well as on static parameters. Different delay values are possible for separate simulation instants. Results can be very accurate in a wide range of operating conditions. | |
| Non-deterministic They find bounds for the delay. They enable simulation of random phenoma but the results obtained are often pessimistic. | Minimum-maximum Assign the same probability to every delay value within a range. |
| Statistical The probability of a delay value is ruled by a probability function, usually Gaussian. |
