TABLE OF CONTENTS In this section, we present a set of characterization results for several CMOS gates in a 0.35 urn technology. All the results have been obtained according to the procedure described in the previous section, using the automatic characterization program autoddm [Juan et al. (2001)]. The analysis of the results obtained will allow us to validate the model and to explore the possibilities of simplifying the model and the characterization process itself.
As an example, we have characterized the values of the gate-level degradation parameters corresponding to the exhaustive model of an inverter and NOR and NAND gates from two to four inputs. The data make up a representative group which will allow us to analyse the behaviour of the degradation parameters when we move from one gate's input to another. The results are shown in Table 5.8 to Table 5.14. The values of the parameters have been ordered in matrix form according to the way indicated in Eq. (5.9) and Eq. (5.10), together with the fitting errors which affect each parameter, ordered in the same way. Likewise, in Fig. 5.5 to Fig. 5.8, the representation of this data is shown for gates with three and four inputs which are those that benefit the most from this representation. In each figure, the column on the left shows, for Type 1 collisions, the variation of each parameter when varying the index of the input on which the transitions take place. The column on...
