4.1 Introduction

We have seen in previous chapter that the propagation delay of a CMOS inverter including the degradation effect can be accurately modelled by using three parameters ( t _{p 0}, ? and T ₀) for each type of input transition. These parameters, in turn, depend on the internal and external conditions of the gate [Juan et al. (1997b)].

The main objective of this chapter is to study the dependence of the three mentioned parameters on those variables that characterize the internal structure of the gate the transistor geometry and the external conditions output load, input waveform and supply voltage. In this chapter, basic equations for these dependencies will be introduced, allowing for the application of the model in two different scenarios: logic simulation at the transistor level, needed for full-custom designs, and logic simulation at the gate level, which is appropriate for semi-custom, library-based designs. In the first case, the equations derived in this chapter may be applied; in the second case, they are the starting point for a characterization process of library cells, developed in the next chapter.

In the next section, the concepts and parameters needed to characterize a CMOS process for logic simulation will be presented and ranges of interest for the model will be stated. The third section presents the delay model for the CMOS inverter presented by Daga et al. [Daga et al. (1996b)] which will be used as an adequate model...