5.1 Introduction

In previous chapters a very accurate model of the degradation effect has been developed for the CMOS inverter at a technological level. Once parameters a, b and c in Eq. (4.17) and Eq. (4.18) have been obtained, the necessary expressions are available to obtain the value of higher level degradation parameters. This delay is expressed as a function of the inverter structure ( W _N and W _P) and the external conditions to the gate: supply voltage, output load and input transition time.

The objective of this chapter is to extend the usability of DDM to more complex CMOS gates than was possible with the CMOS inverter. More precisely, static NAND and NOR gates with an arbitrary number of inputs will be considered. This extension will lead to a more general degradation delay model suitable to be implemented in logic timing simulators, allowing for the analysis of a wide range of digital CMOS circuits taking account of degradation effect [Juan et al. (2000a); Juan et al. (2000b)].

Most delay models for CMOS gates rely on the fact that for every input event causing the switching of the output, it is possible to find an equivalent situation in a simpler gate which is well characterized and easier to analyse. In most cases, the reference gate is the inverter. Therefore, the problem is reduced to obtaining the parameters of the equivalent inverter for the given input event...