TABLE OF CONTENTS As mentioned before, an attempt will be made to extent the DDM to multi-input gates following an external gate-level approach. To do that, it will be necessary to obtain delay equations including the degradation effect and the dependence on external conditions to the gate: supply voltage, input transition time and output load. These equations will also include a set of parameters whose values are gate specific which determine the behaviour of the gates with respect to the degradation effect as it can be seen from the outside of the gate.
For the sake of simplicity, the focus will be on the two main types of gates in CMOS technology: NAND and NOR, as well as the inverter, which is a particular case of both. Although the interest is in modelling the degradation effect, we will also provide gate-level expressions will also be provided for the normal propagation delay based in the model presented in [Daga et al. (1996a)] which has been used in previous chapters.
In a first step a general degradation model will be proposed for gates based on the DDM for the inverter presented in previous chapter. Gate-level parameters will be defined in these general equations. Then, all the input conditions that may lead to degradation effect will be identified and a set of values for each such condition will be defined.
As a starting point, the same basic degradation equation for the inverter in Eq. (5.1) is proposed...
