From Logic-Timing Simulation and the Degradation Delay Model

5.3 Degradation Parameter Characterization Process

In the previous section a complete delay model was proposed for multi-input NOR and NAND gates including the degradation effect. The model takes into account the following external variables: supply voltage, output load, input transition time and the time since the last output change. The set of parameters for an exhaustive characterization of a gate considering all the input collisions has also been analysed. The purpose of this section is to validate the proposed model. In a first step we will verify that the general model in Eq. (5.1) fits the behaviour of multi-input gates, as it did for the inverter. Secondly, a procedure to extract the gate-level degradation parameters of a gate will be set up, obtaining the matrices of degradation parameters , and corresponding to Eq. (5.11) and Eq. (5.12). The complexity of the characterization process that will illustrate the suitability of the approach to practical applications will also be analysed.

5.3.1 General Degradation Model Validation

For each glitch input collision to a multi-input gate, it is possible to obtain a delay degradation curve as we did for the CMOS inverter in Sec. 3.2.2 (Fig. 3.5). The procedure consists of providing two consecutive input transitions and measuring, by electrical simulation, the propagation delay due to the second transition ( t p), as well as the time elapsed since the first output transition ( T). This method is depicted in Fig. 5.1. By varying the gap between input transitions...

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5.4 Analysis of Results In this section, we present a set of characterization results for several CMOS gates in a 0.35 urn technology. All the results have been obtained according to the procedure...

5.7 Discussion of Results In this Chapter we have presented the extension to the gates of the degradation delay model for the CMOS inverter analysed in Chapters 3 and 4. This extension has been made...

Jorge Juan Chico Alejandro Mill n Calder n 5.1 Introduction In previous chapters a very accurate model of the degradation effect has been developed for the CMOS inverter at a technological level.

5.5 Simplified Model Equations For Type 1 collisions there are no changes with respect to the exhaustive model and we must define a value of each degradation parameter for each input. Therefore, the...

Jorge Juan Chico Alejandro Mill n Calder n 4.1 Introduction We have seen in previous chapter that the propagation delay of a CMOS inverter including the degradation effect can be accurately modelled...