TABLE OF CONTENTS In the previous section a complete delay model was proposed for multi-input NOR and NAND gates including the degradation effect. The model takes into account the following external variables: supply voltage, output load, input transition time and the time since the last output change. The set of parameters for an exhaustive characterization of a gate considering all the input collisions has also been analysed. The purpose of this section is to validate the proposed model. In a first step we will verify that the general model in Eq. (5.1) fits the behaviour of multi-input gates, as it did for the inverter. Secondly, a procedure to extract the gate-level degradation parameters of a gate will be set up, obtaining the matrices of degradation parameters , 
and 
corresponding to Eq. (5.11) and Eq. (5.12). The complexity of the characterization process that will illustrate the suitability of the approach to practical applications will also be analysed.
For each glitch input collision to a multi-input gate, it is possible to obtain a delay degradation curve as we did for the CMOS inverter in Sec. 3.2.2 (Fig. 3.5). The procedure consists of providing two consecutive input transitions and measuring, by electrical simulation, the propagation delay due to the second transition ( t p), as well as the time elapsed since the first output transition ( T). This method is depicted in Fig. 5.1. By varying the gap between input transitions...
