OVERVIEW

Academic researchers, system-on-chip (SOC) designers, and ASIC and EDA vendors are in a fair amount of agreement as to what must be done to reduce SOC design risks. SOC designs must become flexible enough to accommodate design changes brought on by design errors, spec changes, standards changes, and competitive market forces. Designing additional flexibility into an SOC allows one chip design to serve several products and multiple product generations.

One way to add flexibility to an SOC is to add firmware programmability through microprocessor cores. However, firmware programmability alone does not provide the requisite flexibility because general-purpose microprocessor cores with fixed ISAs (instruction-set architectures) often cannot meet system performance requirements.

As discussed in Chapter 1, the popular way to extract higher performance from a fixed-ISA microprocessor is to boost its clock rate. This approach worked in the PC market, as x86 processor clock rates rocketed from 4.77MHz to more than 3GHz over two decades. However, high clock rates incur a power-dissipation penalty that increases exponentially with clock rate, which was also discussed in Chapter 1. This chapter and subsequent chapters provide an introduction to a processor ISA that s more appropriate for SOC design: Tensilica s Xtensa microprocessor ISA.

In its basic form, Tensilica s Xtensa processor core is a small, fast 32-bit processor core with industry-leading performance. Unlike most other processor cores available to SOC designers, the Xtensa core can be tuned to a very...