TABLE OF CONTENTS Anything you can do, I can do better. I can do any thing better than you!
Annie Oakley in Annie Get Your Gun, 1946
Because many applications just don t run fast enough on standard embedded microprocessor cores even with an auxiliary DSP core, engineering teams have hand-coded parts of many SOC designs in Verilog or VHDL to achieve system-level performance goals. However, custom, manually-coded RTL logic takes a long time to design and longer to verify. In addition, RTL blocks can t be easily changed once they re designed because of verification issues, yet changes are often needed to accommodate new standards or product features.
Configurable processors like Tensilica s Xtensa cores can be used as alternatives to manually-coded RTL blocks. Application-tailored Xtensa cores use the same data-path structures as traditional RTL blocks: deep pipelines, parallel execution units, task-specific state registers, and wide data buses to local and global memories. Tailored, task-specific processors can sustain the same high-computation throughput and support the same data interfaces as RTL hardware designs.
Migrating an SOC design team s design style from heavy use of RTL data paths and finite state machines (FSMs) to application-tailored processors with firmware control has many important implications:
Flexibility: changing the firmware is all that s needed to change a block s function.
Software-based development: Fast and low-cost software tools can be used to implement or modify most chip features.
Faster, more complete system modeling: For a 10-megagate design, even the fastest...
