OVERVIEW

The Diamond 570T CPU core is a high-performance, 3-way static-superscalar RISC CPU core. The term superscalar describes a processor that achieves superlative performance by executing multiple scalar instructions per clock cycle. Just as warp engines allow the Starship Enterprise to break the speed-of-light barrier, superscalar execution pipelines allow the Diamond 570T CPU to break the 1-instruction-per-clock barrier that limits conventional scalar RISC architectures. Scalar instructions are the instructions found in the ISAs of most general-purpose processors including the Xtensa ISA. Superscalar processor implementations are a viable alternative to increasing clock rates (which unacceptably increase power dissipation). Rather than execute more instructions per second through clock-rate escalation, superscalar processors execute multiple instructions per clock cycle through parallel execution pipelines.

Most superscalar microprocessor designs are of the dynamic superscalar type. Dynamic superscalar processors contain logic that examines the incoming scalar instruction stream and seeks to group independent scalar instructions into bundles of instructions that can be executed concurrently. Processor designers take the dynamic superscalar approach to accelerate any scalar code that might have been written for scalar versions of the target ISA.

The Diamond 570T CPU core is a static-superscalar design. It adds two 64-bit instruction formats to the existing 16- and 24-bit Xtensa ISA instruction formats, as shown in Figure 10.1. The Diamond 570T processor s first 64-bit instruction format contains two operation slots. The instructions first slot accommodates base Xtensa instructions. The...