Designing SOCs with Configured Cores: Unleashing the Tensilica Xtensa and Diamond Cores

The requirement for processing power will be 1000 in the next ten years.
International Technology Roadmap for Semiconductors: 2005.
Designer-defined Xtensa processor cores and pre-configured Diamond cores are SOC building blocks. It s critically important for the SOC design team to have the most flexible building blocks available to maximize the team s ability to reach project performance goals while staying within budget and on schedule. However, it s also critically important for the design team to employ productive system-design strategies that effectively and efficiently use those building blocks. Many SOC design teams employ system-design strategies rooted in the previous century. These design strategies were developed when ASIC gate counts were in the hundreds of thousands, long before SOCs broke the million-gate threshold. Consequently, these strategies are now obsolete. They cannot make the design-team members sufficiently productive to produce mega-gate SOC designs economically.
The organization that perhaps pays more attention to chip-level system-design-strategies than any other in the world is the ITRS (International Technology Roadmap for Semiconductors). The ITRS assesses all semiconductor technology requirements (for design, manufacturing, and reliability) to ensure continued global advancements in integrated circuit performance. This assessment, which produces a new industry road map every two years, is a worldwide cooperative effort of the industry s manufacturers and suppliers, government organizations, consortia, and universities. It is the way that the semiconductor industry has chosen to map the route for the continued enforcement of Moore s law.
The ITRS continually assesses the available design technologies, technology...