Designing SOCs with Configured Cores: Unleashing the Tensilica Xtensa and Diamond Cores

Chapter 5: MPSOC System Architectures and Design Tools

In pioneer days they used oxen for heavy pulling, and when one ox couldn t budge a log, they didn t try to grow a larger ox. We shouldn t be trying for bigger computers, but for more systems of computers.

Admiral Grace Hopper

If you were plowing a field, which would you rather use: Two strong oxen or 1024 chickens?

Seymour Cray

OVERVIEW

All SOC architectures in the 21st century will consist of many interconnected hardware blocks. There s simply no other possible design approach that can reconcile the complexity of mega-gate SOCs with the mental abilities and capacities of human designers. Many SOC blocks will contain memories, some will consist of custom-designed logic, some will be pre-designed IP, and some will be microprocessor cores. These blocks will intercommunicate over a variety of buses, networks, and point-to-point connections. This chapter ties a number of concepts discussed in previous chapters into an integrated approach to multiple-processor SOC (MPSOC) design.

As previous chapters have already discussed, custom-designed, hand-built logic blocks are usually not programmable and are therefore not flexible. Fixed-ISA microprocessor cores are programmable and flexible but they sometimes lack the processing capability and I/O bandwidth needed to perform a task. Configurable processors share the flexibility and programmability of fixed-ISA microprocessor cores while enabling substantial task-specific computational performance and I/O bandwidth improvements through their extreme hardware flexibility and adaptability. Therefore, you should expect to see a rise in the number of programmable fixed-ISA and configurable microprocessor cores used in each SOC design as design teams...

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