SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

Chapter 1: Verification Guidelines

"Some believed we lacked the programming language to describe your perfect world "
(The Matrix, 1999)

1.1 Introduction

Imagine that you are given the job of building a house for someone. Where should you begin? Do you start by choosing doors and windows, picking out paint and carpet colors, or selecting bathroom fixtures? Of course not! First you must consider how the owners will use the space, and their budget, so you can decide what type of house to build. Questions you should consider are; do they enjoy cooking and want a high-end kitchen, or will they prefer watching movies in the home theater room and eating takeout pizza? Do they want a home office or extra bedrooms? Or does their budget limit them to a basic house?

Before you start to learn details of the SystemVerilog language, you need to understand how you plan to verify your particular design and how this influences the testbench structure. Just as all houses have kitchens, bedrooms, and bathrooms, all testbenches share some common structure of stimulus generation and response checking. This chapter introduces a set of guidelines and coding styles for designing and constructing a testbench that meets your particular needs. These techniques use some of the same concepts as shown in the Verification Methodology Manual for SystemVerilog (VMM), Bergeron et al. (2006), but without the base classes.

The most important principle you can learn as a verification engineer is: "Bugs are good." Don't shy away from finding the next...

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