SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

6.10: Constraints Tips and Techniques

6.10 Constraints Tips and Techniques

How can you create constrained-random tests that can be easily modified? There are several tricks you can use.

6.10.1 Constraints with Variables

Most constraint examples in this book use constants to make them more readable. In Example 6-25, size is randomized over a range that uses a variable for the upper bound.

Example 6-25: Constraint with a variable bound
class bounds;  rand int size;  int max_size = 100;  constraint c_size {   size inside {[1:max_size]};  }endclass

By default, this class creates random sizes between 1 and 100, but by hanging the variable max_size, you can vary the upper limit.

You can use variables in the dist constraint to turn on and off values and anges. In Example 6-26, each bus command has a different weight variable.

Example 6-26: dist constraint with variable weights
typedef enum (READ8, READ16, READ32) read_t;class ReadCommands;  rand read_t read_cmd;  int read8_wt=1, read16_wt=1, read32_wt=1;  constraint c_read {    read_cmd dist {READ8  := read8_wt,                   READ16 := read16_wt,                   READ32 := read32_wt};    }endclass

By default, this constraint produces each command with equal probability. If you want to have a greater number of READ8 commands, increase the read8_wt weight variable.

UNLIMITED FREE
ACCESS
TO THE WORLD'S BEST IDEAS

SUBMIT
Already a GlobalSpec user? Log in.

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.

Customize Your GlobalSpec Experience

Category: Capacitors
Finish!
Privacy Policy

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.