TABLE OF CONTENTS The random stimulus generation in SystemVerilog is most useful when used with OOP. You first create a class to hold a group of related random variables, and then have the random-solver fill them with random values. You can create constraints to limit the random values to legal values, or to test specific features.
Note that you can randomize individual variables, but this case is the least interesting. True constrained-random stimuli is created at the transaction level, not one value at a time.
Example 6-1 shows a class with random variables, constraints, plus testbench code to use this class.
class Packet; // The random variables rand bit [31:0] src, dst, data[8]; randc bit [7:0] kind; // Limit the values for src constraint c {src > 10; src < 15;}endclassPacket p;initial begin p = new; // Create a packet assert (p.randomize()); transmit(p);end This class has four random variables. The first three use the rand modifier, so that every time you randomize the class, the variables are assigned a value. Think of rolling dice: each roll could be a new value or repeat the current one. The kind variable is randc, which means random cyclic, so that the random solver does not repeat a random value until every possible value has...
