SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

6.4: Constraint Details

6.4 Constraint Details

Useful stimulus is more than just random values there are relationships between the variables. Otherwise, it may take too long to generate interesting stimulus values, or the stimulus might contain illegal values. You define these interactions in SystemVerilog using constraint blocks that contain one or more constraint expressions. SystemVerilog solves these expressions concurrently, choosing random values that satisfy all the expressions.

Common Mistakes

At least one variable in each expression should be random, either rand or randc. The following class fails when randomized. The solution is to add the modifier rand or randc to the variable son.

The randomize function tries to assign new values to random variables and to make sure all constraints are satisfied. In Example 6-2, since there are no random variables, randomize just checks the value of son to see if it is in the bounds specified by the constraint c_teenager. Unless the variable happens to fall in the range of 13:19, randomize fails.

Example 6-2: Constraint without random variables
class bad;  bit [31:0] son;  // Error - should be rand or randc  constraint c_teenager {son > 12;                         son < 20;}endclass

6.4.1 Constraint Introduction

The following sections use this example of a random class with constraints. The specific constructs are explained later in this section.

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